1. Field
The present embodiments relate generally to semiconductor devices, and more particularly to a photodiode forming a CMOS image sensing device, a solid state image sensor, and a method of manufacturing the same.
2. Description of the Related Art
Nowadays, CMOS image sensing devices are widely used in cellular phones with a camera, digital still cameras, etc. Compared with CCD image sensing devices, CMOS image sensing devices have the preferable characteristics of being simple in configuration and formable at low cost.
FIG. 1 shows a configuration of such a CMOS image sensing device 100.
Referring to FIG. 1, the CMOS image sensing device 100 has a light-receiving region 101A where multiple light-receiving elements 10 are arranged in a matrix manner. A row selector circuit 101B and a signal readout circuit 101C cooperate with each other with respect to each light-receiving element 10. Here, the row selector circuit 101B selects a reset control line RST and a selection control line SEL, while the signal readout circuit 101C supplies a reset voltage to a reset voltage line VR and reads out a signal voltage from a pixel output to a signal readout line SIG.
FIG. 2 shows a configuration of the light-receiving element 10 of one pixel used in the CMOS image sensing device 100 of FIG. 1.
Referring to FIG. 2, a photodiode 10D is connected in a reverse-biased direction to a power supply terminal 10A, which is connected to the reset voltage line VR so as to have a predetermined reset voltage supplied thereto, through a reset transistor 10B controlled by a reset signal on the reset control line RST. Photoelectrons formed by light exposure in the photodiode 10D are converted into voltage by a readout transistor 10F forming a source follower circuit driven by supply voltage from the power supply terminal 10A, and are output. The output is output onto the signal line SIG by a selection transistor 10S connected in series to the readout transistor and controlled by a selection control signal on the selection control line SEL.
FIG. 3A is a plan view showing a configuration of a photodiode 100D used in such a CMOS image sensing device according to the related art of the present invention. FIG. 3B is a cross-sectional view of the photodiode taken along the line X-X′. The photodiode 100D of FIGS. 3A and 3B is used as the photodiode 10D in the CMOS pixel element 10 of FIG. 2.
Referring to FIGS. 3A and 3B, the photodiode 100D is formed on a p-type silicon substrate 111. A device region that defines the photodiode 10D with an isolation insulating film 112 by LOCOS and a p-type channel stopper region 112A thereunder is formed on the p-type silicon substrate 111. Further, an n− diffusion region 111A is formed as a light-receiving region in the device region.
At the operating time of the photodiode 100D, a depletion layer is formed by reverse bias in the light-receiving region 111A so that photoelectrons formed in the light-receiving regions 111A reach a signal electrode, thereby forming a light signal. At this point, in order to increase the sensitivity of the photodiode, the light-receiving region 111A is required to be extremely low in defect density so as to minimize generation of dark current due to thermionic emission and prevent the formed photoelectrons from being captured to disappear on the way or prevent thermions from being emitted into the photoelectrons.
Therefore, according to the configuration of FIGS. 3A and 3B, a p-type guard ring 112B is formed between the light-receiving region 111A and the LOCOS oxide film 112 so as to avoid direct contact of the n− diffusion region 111A with the surface of the isolation insulating film 112. Further, a p-type shield layer 111D is also formed in the surface part of the silicon substrate 111, that is, the surface part of the light-receiving region 111A, thereby avoiding exposure of the light-receiving region at the surface of the silicon substrate 111 containing defects.
Further, an n+ diffusion region 111C is formed so as to be surrounded by the p-type shield layer 111D in part of the surface part of the light-receiving region 111A as a contact layer with the signal electrode. In general, such an n+ diffusion region 111C contains defects at high density. Accordingly, an n-type diffusion region 111B is formed so as to cover the contact layer 111C in the n− light-receiving region 111A, thereby avoiding direct contact of the light-receiving region 111A and the n+ contact layer 111.
Further, a thermal oxide film 113 is formed on the surface of the silicon substrate 111, and a CVD oxide film 114 is further formed thereon. An interlayer insulating film 115 is formed on the CVD oxide film 114. A via plug 116 is formed in the interlayer insulating film 115 so as to be in contact with the contact layer 111C. A signal electrode 117 is formed in contact with the via plug 116 on the interlayer insulating film 115.
FIG. 4 shows the vicinity of the n-type diffusion region 111B of FIG. 3B on an enlarged scale.
Referring to FIG. 4, the depletion region extending from a junction interface PN1 of the p-type silicon substrate 111 and the n− light-receiving region 111A extends over the substantially entire light-receiving region 111A, so that an end part A of the depletion region in the n-side region reaches as far as the n-type diffusion region 111B. Further, the depletion region extending from a junction interface PN2 of the n− light-receiving region 111A and the p-type shield layer 111D is formed so as to combine with the depletion region extending from the junction interface PN1 to have an end part C positioned near the interface PN2 with the light-receiving region 111A in the shield layer 111D.
It is necessary for the contact layer 111C to realize good ohmic junction with the via plug 116. Therefore, the contact layer 111C is heavily doped. On the other hand, a defect D such as dislocation is likely to be caused in this heavily-doped contact layer 111C. Therefore, if the depletion region extends so that its end part A goes beyond the defect D as shown in FIG. 4, carriers such as photoelectrons generated in the depletion region are captured so that leakage current is generated. Further, a large electric field is formed between the heavily-doped contact layer 111C and the p-type shield layer 111D, causing a problem in that leakage current is also likely to be generated in this part. Such leakage current forms dark current so as to decrease the sensitivity of the photodiode.
Further, according to the related art in FIG. 4, the contact layer 111C is formed to be large with respect to the diameter of the via plug 116 so as to ensure allowance for alignment error. However, since the contact layer 111C, in which no depletion region is formed, or the n-type region 111B, which the depletion region hardly enters, takes no part in light receiving, it is necessary to reduce the dimension W of these parts as much as possible in order to increase the photoelectric conversion efficiency of the photodiode 10D.
Meanwhile, FIG. 5 shows the configuration of a conventional photodiode 100E described in Patent Document 1 and Patent Document 2. In FIG. 5, the parts corresponding to those described above are given the same reference numerals, and a description thereof is omitted. Further, in FIG. 5, only parts necessary for description are graphically illustrated, and a graphical illustration of the other parts is omitted.
Referring to FIG. 5, in the photodiode 100E, the n-type diffusion region 111B is formed so as to envelop the n+ contact layer 111, so that the extension of the depletion region from the junction interface PN1 not graphically illustrated is substantially blocked by the n-type diffusion region 111B and prevented from reaching the contact layer 111C containing defects. Further, the depletion region formed at the interface between the shield layer 111D and the n-type diffusion region 111B is confined in the vicinity of the interface and prevented from reaching the contact layer 111C because of the high impurity densities of the layers 111B and 111D. Further, since the n-type diffusion region 111B, lower in impurity density than the n+ contact layer 111C, is interposed between the n+ contact layer 111C and the p-type shield layer 111D, leakage current is prevented from being generated between the contact layer 111C and the shield layer 111D.
Thus, the configuration of FIG. 5 produces an excellent effect in reducing dark current, but has a problem in that the extent of the depletion region extending from the junction interface PN1 is limited so as to reduce the photoelectric conversion efficiency because the n-type diffusion region 111B extends up to the part under the p-type shield layer 111D. Further, in such a structure, the photoelectric conversion efficiency is not improved no matter how much the contact layer 111 may be microfabricated by increasing the accuracy of patterning, unless the diffusion region 111B is reduced in size. However, as long as the diffusion region 111B is formed so as to be in contact with the lower surface of the shield layer 111D, the fabrication of the diffusion region 111B has its limits.
[Patent Document 1] Japanese Laid-Open Patent Application No. 2000-312024
[Patent Document 2] Japanese Laid-Open Patent Application No. 2004-312039